General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
falling edge of the clock pulse. Data on the J and K inputs
may be changed while the clock is HIGH or LOW without
affecting the outputs as long as the setup and hold times
are not violated. A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
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74LS109 Dual J-K Positive-edge-triggered Flip-Flop IC
₨ 145 Original price was: ₨ 145.₨ 120Current price is: ₨ 120.

N Male Connector to BNC Female connector
₨ 1250 Original price was: ₨ 1250.₨ 850Current price is: ₨ 850.
74ls112 ic
₨ 135 Original price was: ₨ 135.₨ 100Current price is: ₨ 100.
Category: IC,S
Description
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Easy interface to all microprocessors
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On-chip clock generator
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0.3[Prime] standard width 20-pin DIP package
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Watchdog Timer: 500 nA, typical
Timer1 Oscillator: 500 nA @ typical 32 kHz Flexible Oscillator Structure
Precision 16 MHz internal oscillator block:
Factory calibrated to 1%
Software selectable frequencies range of 31 kHz to 16 MHz
64 MHz performance available using PLL
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Two external Clock modes up to 64 MHz
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