74LS164 8-Bit Serial Shift Register P
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It is a TTL logic IC from the 74LS (Low‑Power Schottky) family.
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It functions as an 8‑bit serial‑input, parallel‑output shift register. Data is input one bit at a time via serial inputs, shifted in with each clock pulse, and can be read in parallel on 8 output pins.
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Has gated serial inputs and asynchronous clear/reset. The gated inputs (usually two inputs, A and B) allow more control: either input being LOW can inhibit new data (or reset the first flip‑flop on next clock) etc.
Key Specifications
| Parameter | Typical / Max Value |
|---|---|
| Supply Voltage (Vcc) | ~5 V (4.75‑5.25 V) |
| Clock Frequency | up to ~36 MHz in many versions |
| Inputs / Outputs | Two serial data input pins (A, B); 8 parallel outputs (Q0‑Q7) |
| Reset / Clear | Asynchronous clear / master reset (active low) to zero outputs regardless of clock |
| Package | 14‑pin DIP or equivalent (SOIC etc.) |
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