General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
falling edge of the clock pulse. Data on the J and K inputs
may be changed while the clock is HIGH or LOW without
affecting the outputs as long as the setup and hold times
are not violated. A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
-26%
74LS109 Dual J-K Positive-edge-triggered Flip-Flop IC
Original price was: ₨ 145.₨ 120Current price is: ₨ 120.
N Male Connector to BNC Female connector
Original price was: ₨ 1250.₨ 850Current price is: ₨ 850.
74ls112 ic
Original price was: ₨ 135.₨ 100Current price is: ₨ 100.
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